Hazard Hustle — Pipeline Hazard Simulator

ASSUMPTIONS

• RAW hazards only — Read After Write data hazards are simulated
• No structural hazards — separate instruction & data memory assumed
• No control hazards — branch/jump hazards not simulated
• Stalls between ID and EX — hazard detected at decode stage
• Split-phase register access — configurable below (WB writes first half, ID reads second half of same cycle when ON)
• In-order pipeline — instructions execute in program order

INSTRUCTIONS

PIPELINE CONFIG

IF → ID → EX → MEM → WB

Data Forwarding

EX→EX, MEM→EX bypass

Split-Phase Register Access

WB first half, ID second half (same cycle OK)

CONTROLS

SPEED

—

CURRENT CYCLE

LEGEND — FULL FORMS

PIPELINE STAGES

IFInstruction Fetch — fetch the instruction from memory using the program counter

IDInstruction Decode — decode opcode and read source registers from the register file

EXExecute — ALU performs the arithmetic/logic computation or address calculation

MEMMemory Access — read or write data from/to the data cache (used by LW/SW)

WBWrite-Back — write the result back into the destination register

MEM/WBCombined Memory + Write-Back stage (4-stage pipeline only)

STALLPipeline Stall — a bubble injected to wait for a data dependency to resolve

INSTRUCTIONS

ADDAdd — adds two source registers: dest = src1 + src2

SUBSubtract — subtracts registers: dest = src1 − src2

LWLoad Word — loads a 32-bit word from memory into a register: dest = Mem[base + offset]

SWStore Word — stores a register value into memory: Mem[base + offset] = src

HAZARD TYPES

RAWRead After Write — a later instruction tries to read a register before an earlier instruction has finished writing it. This is a data hazard.

EX HazardExecute-stage hazard — the producing instruction is in EX when the consuming instruction needs the value in EX. With forwarding, the EX result is forwarded directly (0 stalls). Example: ADD R1,R2,R3 followed by SUB R4,R1,R5 — I2 reads R1 which I1 writes; I1 is in EX when I2 reaches EX.

MEM HazardMemory-stage hazard — the producer is in MEM when the consumer needs the value in EX. With forwarding, the MEM result is forwarded (0 stalls for ALU; 1 stall for LW since data is only available after MEM, not during EX). Example: LW R6,0(R4) followed by ADD R7,R6,R1 — I2 needs R6 which I1 loads from memory; since the loaded value is only ready after I1's MEM stage, 1 stall is unavoidable even with forwarding.

SYMBOLS & NOTATION

I1, I2…Instruction number in sequence (I1 = first instruction)

CnClock cycle number (C1 = first cycle, C2 = second, etc.)

R0…R7General-purpose registers in the CPU register file

←FWDData forwarding — value bypassed directly from an earlier pipeline stage without waiting for WB

STALLPipeline bubble — one wasted cycle inserted between ID and EX to wait for data

✓ OKHazard resolved with no stalls — data ready in time

destDestination register — the register that receives the result

src1/2Source register(s) — the registers whose values are read as inputs

offsetImmediate byte offset added to the base register for memory address calculation

baseBase register whose value forms the base memory address in LW/SW

CONCEPTS

WITHOUT FORWARDING — Split Access ON (default)

I1: IF → ID → EX → MEM → WB
I2: IF → S → S → ID → EX → MEM → WB

Stalls are inserted between IF and ID so that ID (register read) is delayed until the producer's WB has written the register. With split-phase access, ID can occur in the same cycle as WB (WB writes first half, ID reads second half) — so 2 stalls are needed for a 5-stage pipeline.

WITHOUT FORWARDING — Split Access OFF

I1: IF → ID → EX → MEM → WB
I2: IF → S → S → S → ID → EX → MEM → WB

Without split-phase access, ID must occur strictly after WB completes — one additional stall is required. 3 stalls for a 5-stage pipeline, 2 stalls for 4-stage.

WITH FORWARDING — ALU→ALU (EX or MEM Hazard)

I1: IF → ID → EX → MEM → WB
I2: IF → ID → EX ←FWD → MEM → WB

With forwarding, the ALU result from I1's EX stage is forwarded directly to I2's EX stage — no stalls needed. Layout is unchanged: IF → ID → EX → MEM → WB.

WITH FORWARDING — LW Load-Use Hazard

I1 (LW): IF → ID → EX → MEM → WB
I2: IF → ID → S → EX ←FWD → MEM → WB

LW produces its value after MEM, not EX. Even with forwarding, 1 unavoidable stall is inserted between ID and EX of the consumer. The MEM result is then forwarded to EX (MEM→EX path).

PIPELINE EXECUTION TABLE

⚙

Add instructions and press SIMULATE

HAZARD ANALYSIS

Run simulation to detect hazards